Dataset Viewer
cr
stringlengths 22
57
| start_time
stringdate 2023-11-29 13:40:00
2024-12-04 14:42:00
| end_time
stringdate 2023-11-29 13:57:00
2024-12-04 14:47:00
| device
stringclasses 5
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|---|---|---|---|
V2-CR4-expect_fail-skipped_1620.pdf
|
2024-12-04 14:42:00
|
2024-12-04 14:47:00
|
CORE, DIST1, DIST2, ACC1, ACC2, F5 BIG-IP i4800 HA Cluster, Catalyst 9300 MACSEC switches
|
V2-CR2.4-expect_fail-5_devices_1_performed_extra_step.pdf
|
2024-11-29 13:40:00
|
2024-11-29 13:55:00
|
CORE, DIST1, DIST2, ACC1, ACC2, F5 BIG-IP i4800 HA Cluster, Catalyst 9300 MACSEC switches
|
V2-CR2-expect_pass.pdf
|
2024-11-29 13:40:00
|
2024-11-29 13:55:00
|
CORE, DIST1, DIST2, ACC1, ACC2
|
V2-CR2.1-expect_pass-disordered_steps.pdf
|
2024-11-29 14:00:00
|
2024-11-29 14:10:00
|
CORE, DIST1, DIST2, ACC1, ACC2, F5 BIG-IP i4800 HA Cluster, Catalyst 9300 MACSEC switches
|
V2-CR2.2-expect_fail-1_device_performed_extra_step.pdf
|
2024-11-29 13:40:00
|
2024-11-29 13:55:00
|
F5 BIG-IP i4800 HA Cluster, Catalyst 9300 MACSEC switches
|
V2-CR3-expect_fail-skipped_xiv.pdf
|
2024-12-04 14:42:00
|
2024-12-04 14:47:00
|
CORE, DIST1, DIST2, ACC1, ACC2
|
V2-CR7-expect_pass.pdf
|
2023-11-29 13:40:00
|
2023-11-29 13:57:00
|
CORE switch, DIST1 switch, DIST2 switch, ACC1 switch, ACC2 switch
|
V2-CR8-expect_fail-skipped_line5.pdf
|
2023-12-04 14:40:00
|
2023-12-04 14:48:00
|
CORE switch, DIST1 switch, DIST2 switch, ACC1 switch, ACC2 switch
|
V2-CR6-expect_fail-wrong_mask_610.pdf
|
2024-11-29 13:40:00
|
2024-11-29 13:55:00
|
CORE, DIST1, DIST2, ACC1, ACC2, F5 BIG-IP i4800 HA Cluster, Catalyst 9300 MACSEC switches
|
V2-CR5-expect_fail-wrong_mask_xiii.pdf
|
2024-11-29 13:40:00
|
2024-11-29 13:55:00
|
CORE, DIST1, DIST2, ACC1, ACC2
|
V2-CR2.3-expect_fail-2_devices_1_performed_extra_step.pdf
|
2024-11-29 13:40:00
|
2024-11-29 13:55:00
|
CORE, DIST1, F5 BIG-IP i4800 HA Cluster, Catalyst 9300 MACSEC switches
|
V2-CR1-expect_pass.pdf
|
2024-11-29 13:40:00
|
2024-11-29 13:55:00
|
CORE, DIST1, DIST2, ACC1, ACC2
|
V2-CR9-expect_fail-wrong_mask.pdf
|
2023-11-29 13:40:00
|
2023-11-29 13:57:00
|
CORE switch, DIST1 switch, DIST2 switch, ACC1 switch, ACC2 switch
|
README.md exists but content is empty.
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